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microTECH Global LTD
Cambridge
Job DescriptionMy client design cutting-edge ASICs that sit at the heart of our world-leading precision timing products. We are looking for a Senior ASIC Layout Engineer with the skills and enthusiasm to significantly enhance the competitive position by delivering robust, high-performance custom analogue and mixed-signal integrated circuits.About t
Job Source: microTECH Global LTDEnterprise Recruitment Ltd
Cambridge
We are looking for a Senior ASIC Layout Engineer in Cambridge to work for a global developer of highly precise technology used in space and telecom markets. On offer is an above market rate salary, bonus scheme (both personal and company), private health insurance, generous pension, flexible working conditions (both hours and offshore opportunities
Job Source: Enterprise Recruitment LtdRakon
Cambridge, England, United Kingdom
Senior ASIC Layout Engineer - Hybrid Working At Rakon, we design cutting-edge oscillator ASICs that sit at the heart of our world-leading precision timing products. We take immense pride in pushing the limits of design to deliver products that are several years ahead of the current market. To complement our growing ASIC team, we are looking for a S
Job Source: RakonRakon
Cambridge
Job Description Senior ASIC Layout Engineer - Hybrid Working At Rakon, we design cutting-edge oscillator ASICs that sit at the heart of our world-leading precision timing products. We take immense pride in pushing the limits of design to deliver products that are several years ahead of the current market. To complement our growing ASIC team, we
Job Source: RakonHanwha Phasor
Cambridge, England, United Kingdom
Principal RF/Analog ASIC Design Engineer Hanwha-Phasor are recruiting a Principal RF/Analog ASIC Design Engineer to work on the specification, architecture design and circuit design of key circuits and sub-systems of integrated RF transceivers for next generation of satellite communications in various deep sub-micron technologies. The Principal RF
Job Source: Hanwha PhasorHanwha Phasor
Cambridge
Job DescriptionPrincipal RF/Analog ASIC Design EngineerHanwha-Phasor are recruiting a Principal RF/Analog ASIC Design Engineer to work on the specification, architecture design and circuit design of key circuits and sub-systems of integrated RF transceivers for next generation of satellite communications in various deep sub-micron technologies. The
Job Source: Hanwha PhasorIC Resources
Cambridge, England, United Kingdom
£85k - £100k Plus Benefits A new opportunity has arisen for a Principal Analog IC Design Engineer to join an established global company working on world leading precision timing products at their new design centre in Cambridge. To further complement their growing Analog IC Design team, they are looking for a Principal Analog IC Designer with the
Job Source: IC ResourcesIC Resources
Cambridge
Job Description£85k - £100k Plus BenefitsA new opportunity has arisen for a Principal Analog IC Design Engineer to join an established global company working on world leading precision timing products at their new design centre in Cambridge. To further complement their growing Analog IC Design team, they are looking for a Principal Analog IC Design
Job Source: IC ResourcesCambridge, England, United Kingdom
My client design cutting-edge ASICs that sit at the heart of our world-leading precision timing products. We are looking for a Senior ASIC Layout Engineer with the skills and enthusiasm to significantly enhance the competitive position by delivering robust, high-performance custom analogue and mixed-signal integrated circuits.
About the client and position:
As an ASIC Layout Engineer, you would play an integral role of bringing the designs into silicon. You will be working closely with the design team and the Layout Lead to decide the layout requirements and achieve the task efficiently and with minimum risk. The ideal layout engineer would have had previous professional experience in a high-volume production environment with a sound understanding of ASIC design and development flow.
Responsibilities:
* Layout of blocks within the ASIC while considering the block interfaces on the top level through good
communication with layout lead and design engineer.
* Running block and top-level layout checks and solve flagged errors.
* Contribute to the layout process continuous improvement by identifying opportunities and participate
in and/or proactively lead initiatives.
* Floor planning of the ASIC.
Requirements:
* A Bachelor, Master or PhD degree in Electronics Engineering or related subject.
* Over 5 years of hands-on experience with analogue circuit layout in CMOS and Bi-CMOS
technologies.
* Be a team player with good interpersonal skills, and excellent communication skills, including verbal,
written and communication, and presentation skills in English.
* Very good knowledge of Cadence tool workflow for schematic capture and layout XL.
* Very good knowledge in running tool for checking DRC, LVS, ERC and antenna rules and ability to
effectively debug any errors
* Very good knowledge of good layout matching techniques such as common centroid or dummy
usage
* Very good understanding of electromigration and how to layout a block with high reliability
* Appreciation and knowledge of parasitic associated with a layout.
* Knowledge of Cadence SKILL language and PCELL development.
Senior Analog ASIC Layout Engineer jobs in Cambridge, England, United Kingdom
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