Formal Verification Engineer
Cambridge, England, United Kingdom
Formal Verification Engineer
We are working with the world's largest CPU development company who are looking to add an experienced Formal Verification Engineer for their systems IP team in Cambridge. This role will allow you to work on the latest hardware design and verification methodologies to develop complex and highly configurable hardware IP that sit at the heart of the company's Systems. This is a permanent role that can be worked on-site in Cambridge, Manchester or Sheffield.
Responsibilities for the role:
Design and build cutting-edge testbenches for next-generation hardware IP.
Optimize existing testbenches for peak performance, quality, and efficiency.
Analyze proposed design changes through a verification lens, ensuring testability.
Take complete ownership of verification environments, from initial setup to successful closure.
Develop, enhance, and maintain robust SVA Formal testbenches.
Craft and refine a comprehensive suite of SVA Protocol Checkers for both formal and simulation use
Requirements for this role:
Formal Verification Architect & Leader: Expertise in architecting, leading, and implementing formal verification environments for intricate IP and module-level designs.
SVA Assertion Master: Proven experience in property-based model checking or Formal Property Verification using SystemVerilog Assertions (SVA) with industry-standard formal tools.
Nice to have:
Team Leadership & Mentorship: Proven ability to lead and mentor teams, fostering growth and collaboration.
Multiprocessing Expertise: Deep understanding of multiprocessing microarchitectures, including cache coherence protocols (AMBA5 CHI, AMBA4 ACE) and bus protocols (AXI).
Collaborative Communicator: Excellent communication skills, adept at working effectively within a team environment.
Keywords: Formal Verification / Formal Methods / SVA / IP / SystemVerilog / System Verilog / AMBA 5 / AXI / Formals / Protocol Checkers / Checkers / Hardware / Systems / Cambridge / UK
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